1. Field of the Invention
The present invention relates to semiconductor devices and a method of manufacturing the same, and more particularly to a semiconductor device having a Bi-CMOS element and a method of manufacturing the same.
2. Description of the Background Art
Conventionally, a Bi-CMOS element is known as one which combines high speed characteristics of a bipolar element and high integration characteristics and low power consumption characteristics of a CMOS element.
FIG. 33 is a cross sectional view showing a semiconductor device having a conventional Bi-CMOS element. Referring to FIG. 33, in the semiconductor device having the conventional Bi-CMOS element, an N-channel MOS transistor, a P-channel MOS transistor, and an NPN bipolar transistor are formed adjacent to each other on a P.sup.- type semiconductor substrate 101. Element isolation regions are provided between the N-channel MOS transistor and the P-channel MOS transistor, and between the P-channel MOS transistor and the NPN bipolar transistor, respectively.
In the N-channel transistor region, a P.sup.+ type buried layer 103 is formed on P.sup.- type semiconductor substrate 101. A P-type well 107 is formed on P.sup.+ type buried layer 103. On a main surface of P type well 107, N.sup.+ type source/drain regions 115a and 115b are formed with a prescribed space so as to sandwich a channel region. On the channel region sides of N.sup.+ type source/drain regions 115a and 115b, N.sup.- type source/drain regions 112a and 112b are formed, respectively. On the channel region a lower polycrystalline silicon film 118c is formed with a gate oxide film 117c interposed therebetween. An upper polycrystalline silicon film 119c is formed on lower polycrystalline silicon 118c. Lower polycrystalline silicon film 118c and upper polycrystalline silicon film 119c constitute a gate electrode. Sidewall oxide films 120c are formed on both side surfaces of lower polycrystalline silicon film 118c and upper polycrystalline silicon film 119c.
In the P-channel MOS transistor region, an N.sup.+ type buried layer 102 is formed on P.sup.- type semiconductor substrate 101. An N-well 106 is formed on N.sup.+ buried layer 102. On a main surface of an N-well 106 P.sup.+ type source/drain regions 114a and 114b are formed with a prescribed space so as to sandwich a channel region. P.sup.- type source/drain regions 111a and 111b are formed respectively on the channel region sides of P.sup.+ type source/drain regions 114a and 114b. On the channel region a lower polycrystalline silicon film 118b formed with a gate oxide film 117b interposed therebetween. An upper polycrystalline silicon film 119b is formed on lower polycrystalline silicon film 118b. Lower polycrystalline silicon film 118b and upper polycrystalline silicon film 119b constitute a gate electrode. Sidewall oxide films 120b are formed on both side surfaces of lower polycrystalline silicon film 118b and upper polycrystalline silicon film 119b.
In the NPN bipolar transistor region, N.sup.+ type buried layer 102 is formed on P.sup.- type semiconductor substrate 101. An N.sup.- type epitaxial layer 104 is formed on N.sup.+ type buried layer 102. In a prescribed region of N.sup.- type epitaxial layer 102, an N.sup.+ type collector electrode drawing-out layer 108 is formed extending from its surface down to N.sup.+ type buried layer 102. On a main surface of N.sup.- type epitaxial layer 104, a P-type base layer 109 and a P.sup.+ external base layer 113 are formed with a prescribed space from N.sup.+ type collector electrode drawing-out layer 108. An N.sup.+ type emitter layer 110 is formed in a prescribed region on a main surface of P type base layer 109. A gate oxide film 117a having an opening on N.sup.+ type emitter layer 110 is formed in a prescribed region on P type base layer 109. A lower polycrystalline silicon film 118a is formed on gate oxide film 117a. An upper polycrystalline silicon film 119a is formed electrically connected to N.sup.+ type emitter layer 110, and extending on and along an upper surface of lower polycrystalline silicon film 118a. Lower polycrystalline silicon film 118a and upper polycrystalline silicon film 119a constitute an emitter electrode. A sidewall oxide film 120a is formed on a sidewall portion of lower polycrystalline silicon film 118a and upper polycrystalline silicon film 119a. An isolation oxide film 116 is formed between N.sup.+ type collector electrode drawing-out layer 108 and P.sup.+ type external base layer 113.
In the element isolation region between the transistors, isolation oxide film 116, a P.sup.+ type element isolation layer 105, and P.sup.+ type buried layer 103 are formed. A surface protection oxide film 121 is formed to cover the whole surface. A contact hole is formed in a region corresponding to an electrode formation region of surface protection oxide film 121. A collector electrode wiring 122, a base electrode wiring 123, an emitter electrode wiring 124, a source/drain electrode wiring 125 of the P-channel MOS transistor, a gate electrode wiring, not shown, of the P-channel MOS transistor, a source/drain electrode wiring 126 of the N-channel MOS transistor, and a gate electrode wiring, not shown, of the N-channel MOS transistor are respectively formed to bury the corresponding contact holes.
Gate oxide films 117a, 117b and 117c are formed to have a thickness of approximately 10 nm, respectively. Lower polycrystalline silicon films 118a, 118b, and 118c are formed to have a thickness of approximately 20-70 nm, respectively. Upper polycrystalline silicon films 119a, 119b and 119c are formed to have a thickness of approximately 150-200 nm , respectively. Surface protection oxide film 121 is formed to have a thickness of approximately 1000 nm.
FIGS. 34 to 39 are sectional views showing a method of manufacturing the semiconductor device including the conventional Bi-CMOS element shown in FIG. 33. The method of manufacturing the semiconductor device including the conventional Bi-CMOS element will now be described with reference to FIGS. 34 to 39.
Initially, as shown in FIG. 34, after arsenic (As) or antimony (Sb) is ion-implanted into the bipolar transistor formation region and the P-channel MOS transistor formation region on P.sup.- type semiconductor substrate 101, heat treatment is carried out, so that N.sup.+ type buried layer 102 is formed. After boron (B) is ion-implanted into the N-channel MOS transistor formation region and the element isolation region, heat treatment is carried out, so that P.sup.+ type buried layer 103 is formed. N.sup.- type epitaxial layer 104 is formed all over the surface. Isolation oxide films 116 are formed in the element isolation regions and the collector-base isolation region of the bipolar transistor, with a LOCOS (LOCal Oxidation of Silicon) method.
The collector electrode formation region of the bipolar transistor is subjected to solid phase diffusion with phosphorus (P) to form N.sup.+ type collector electrode drawing-out layer 108. After boron (B) is ion-implanted through isolation oxide film 116 in the element isolation region, heat treatment is carried out, so that P.sup.+ type element isolation layer 105 is formed.
After phosphorus (P) is ion-implanted into the P-channel MOS transistor region, heat treatment is carried out, so that N-type well 106 is formed. After boron (B) is ion-implanted into the N-channel MOS transistor region, heat treatment is carried out, so that P-type well 107 is formed.
As shown in FIG. 35, after boron (B) is ion-implanted into N.sup.- type epitaxial layer 104 of the bipolar transistor region, heat treatment is carried out, so that P-type base layer 109 is formed.
As shown in FIG. 36, thermal oxidation is performed all over the surface to form gate oxide layer 117 having a thickness of approximately 10 nm. Lower polycrystalline silicon layer 118 having the thickness of approximately 20-70 nm is formed on gate oxide layer 117 by a CVD method. A photoresist 151 is formed in a prescribed region on lower polycrystalline silicon layer 118. Lower polycrystalline silicon layer 118 and gate oxide layer 117 in the emitter formation region of the bipolar transistor are anisotropically etched with photoresist 151 as a mask. Thereafter, photoresist 151 is removed.
As shown in FIG. 37, upper polycrystalline silicon layer 119 having the thickness of approximately 150-200 nm is formed all over the surface by a CVD method. After arsenic (As) is ion-implanted into upper polycrystalline silicon layer 119 and lower polycrystalline silicon layer 118, heat treatment is carried out, so that arsenic is diffused uniformly into upper polycrystalline silicon layer 119 and lower polycrystalline silicon layer 118, and electrically activated. N.sup.+ type emitter layer 110 is thus formed. The ion-implantation of arsenic into upper polycrystalline silicon layer 119 and lower polycrystalline silicon layer 118 is performed under conditions where arsenic ions should not attain gate oxide layer 117.
Lower polycrystalline silicon layer 118 serves as a protection film for gate oxide layer 117 when removing photoresist 151 at the step shown in FIG. 36.
After a photoresist 152 as shown in FIG. 38 is formed in a prescribed region on the upper polycrystalline silicon layer, upper polycrystalline silicon 119 (see FIG. 37) and lower polycrystalline silicon layer 118 (see FIG. 37) are anisotropically etched with photoresist 152 as a mask. As a result, as shown in FIG. 38, lower polycrystalline silicon films 118a, 118b, and 118c and upper polycrystalline silicon films 119a, 119b, and 119c, that is, an emitter electrode constituted of lower polycrystalline silicon film 118a and upper polycrystalline silicon film 119a, a gate electrode constituted of lower polycrystalline silicon film 118b and upper polycrystalline silicon film 119b, and a gate electrode constituted of lower polycrystalline silicon film 118c and upper polycrystalline silicon film 119c are formed. Thereafter, photoresist 152 is removed.
As shown in FIG. 39, a photoresist 153 is formed to cover a region other than the P-channel MOS transistor region. Boron (B) is ion-implanted at a low concentration into the P-channel MOS transistor region is photoresist 153 as a mask, so as to form P.sup.- type source/drain regions 111a and 111b. Thereafter, photoresist 153 is removed.
As shown in FIG. 40, a photoresist 154 is formed to cover a region other than the N-channel MOS transistor region. Phosphorus (P) is ion-implanted at a low concentration into the N-channel MOS transistor region with photoresist 154 as a mask, so as to form N.sup.- type source/drain regions 112a and 112b. Thereafter, photoresist 154 is removed.
As shown in FIG. 41, after oxide film 120 is formed on the whole surface by a CVD method, the whole surface is subjected to anisotropic etching, so that sidewall oxide films 120a, 120b, and 120c and gate oxide films 117a, 117b, and 117c are formed, as shown in FIG. 42.
As shown in FIG. 43, a photoresist 155 is formed to cover a region other than the P-channel MOS transistor region and an external base region of the bipolar transistor. Boron (B) is ion-implanted at a high concentration with photoresist 155 as a mask, so as to form P.sup.+ type external base layer 113 and P.sup.+ type source/drain regions 114a and 114b. Thereafter, photoresist 155 is removed.
As shown in FIG. 44, a photoresist 156 is formed to cover a region other than the N-channel MOS transistor region. Arsenic (As) is ion-implanted at a high concentration with photoresist 156 as a mask, to form N.sup.+ type source/drain regions 115a and 115b. Thereafter, photoresist 156 is removed. Impurities are electrically activated by heat treatment in P.sup.- type source/drain regions 111a and 111b, P.sup.+ type source/drain regions 114a and 114b, N.sup.- type source/drain regions 112a and 112b, N.sup.+ type source/drain regions 115a and 115b, and P.sup.+ external base layer 113. The P-channel MOS transistor and the N-channel MOS transistor each having an LDD structure, and the NPN bipolar transistor are thus completed.
Finally, as shown in FIG. 33, surface protection oxide film 121 having the thickness of approximately 1000 nm is formed all over the surface by a CVD method. A contact hole is formed in a prescribed region of surface protection oxide film 121. After depositing low resistance metal, such as Al, in the contact hole by a sputtering method, pattering is performed to form collector electrode wiring 122, base electrode wiring 123 and emitter electrode wiring 124 of the bipolar transistor, source/drain electrode wirings 125 of the P-channel MOS transistor, source/drain electrode wirings 126 of the N-channel MOS transistor, and gate electrode wirings, not shown, of the P-channel MOS transistor and the N-channel MOS transistor. The semiconductor device having the conventional Bi-CMOS element shown in FIG. 33 is thus formed.
In the method of manufacturing the semiconductor device including the conventional Bi-CMOS element described above, the gate oxide films (117b, 117c) of the MOS transistors and the gate oxide film (117a) of the NPN transistor are formed simultaneously, as well as the gate electrodes (118b, 119b, 118c, 119c) of the MOS transistors and the emitter electrodes (118a, 119a) of the bipolar transistor are formed simultaneously, aiming to simplification of the manufacturing process.
Description will now be made on a parasitic capacitance of a conventional bipolar transistor with reference to FIG. 45. An emitter-base parasitic capacitance Cte of the bipolar transistor is the sum of a junction capacitance Cte.sub.1 of N.sup.+ type emitter layer 110 and P-type base layer 109 and an insulation capacitance Cte.sub.2 of an oxide film 200 insulating an emitter electrode 201 and P-type base layer 109 (Cte=Cte.sub.1 +Cte.sub.2).
In the bipolar transistor portion of the conventional Bi-CMOS shown in FIG. 33, gate oxide film 117a whose thickness is the same as those of gate oxide films 117b and 117c of the MOS transistor portions corresponds to oxide film 200 of FIG. 45. Gate oxide films 117b and 117c are formed to have a very small thickness of approximately 10 nm for enhancing performance of the MOS transistors. Therefore, the gate oxide film 117a is also made to have a very small thickness of approximately 10 nm.
The insulation capacitance Cte.sub.2 is inversely proportional to the thickness of oxide film 200 (gate oxide film 117a). In other words, the smaller the thickness of gate oxide film 117a becomes, the larger the insulation capacitance Cte.sub.2 grows. Accordingly, in the conventional Bi-CMOS structure, the insulation capacitance Cte.sub.2 of the bipolar transistor portion becomes too large, resulting in disadvantageous increase of the emitter-base parasitic capacitance Cte. This leads to decrease of operational speed of the bipolar transistor portion in the Bi-CMOS structure. Such decrease of operational speed on account of increase of the emitter-base parasitic capacitance Cte is disclosed, for example, in Physics of Semiconductor Devices--SECOND EDITION--S. M. Sze, 1981, pp. 158-159. The above problem is peculiar to the Bi-CMOS structure requiring simultaneous formation of the MOS transistor portion and the NPN transistor portion for simplification of the manufacturing process. Ctc shown in FIG. 45 indicates a base-collector capacitance.